![modelsim altera vhdl modelsim altera vhdl](https://smilingspider.files.wordpress.com/2013/01/msconsole.png)
We have that req_if and ack_if defined in a package. My VHDL is super rusty, especially at this sort of level, so I can't remember what the deal is with scope in packages. This api_if looks like probably the req_if that's defined in the package. Wait until (ack_if(bfm_id).ack(MM_MSTR_INIT) = '0') Wait until (ack_if(bfm_id).ack(MM_MSTR_INIT) = '1') Signal api_if : inout mm_mstr_vhdl_if_t) is
#MODELSIM ALTERA VHDL CODE#
In the code we see: procedure init (bfm_id : in integer
#MODELSIM ALTERA VHDL MANUAL#
If we look at the init() function: The reference manual states: VHDL Args are bfm_id, req_if(bfm_id). Then any function that needs bfm_id, pass the correct value for the BFM you are using.Īs for the req_if(bfm_id) thing. Probably start with 0, use 0,1 if you need two masters, etc. So instantiate the altera_avalon_mm_master_bfm_vhdl component, giving it a unique (among other mm masters) VHDL_ID. It creates an array of these records, which are all the signals that you need to pass around. So basically this is Intel faking the SV interface feature. Looking in the VHDL package, you can see the functions all take bfm_id and api_if, then bfm_id is used as an index into api_if.Īlso in the actual vhdl source, note that one of the generics is VHDL_ID, which is used to index: req_if and ack_if, which are signalls defined in the package, which are an array of the record: mm_mstr_vhdl_if_base_t. You'll note there's a altera_avalon_mm_master_bfm folder and a altera_avalon_mm_master_bfm_vhdl folder. Then you can find the source code for the avalan mm master BFM is in:Ĭ:\intelFPGA_lite\18.1\ip\altera\sopc_builder_ip\verificationĪt least for my local install, and version. However, Verilog HDL systems ignore this setting. The parameter appears in the top-level HDL for both Verilog HDL and VHDL files. The VHDL BFM ID is only applicable for VHDL BFMs. You change the ID with the VHDL BFM ID option.
![modelsim altera vhdl modelsim altera vhdl](https://s1.manualzz.com/store/data/012316250_1-d35c56865edf8b2f1f63fe8dd366dcb5.png)
(Optional) Make changes as needed to the BFM, such as changing the BFM instance name or the VHDL BFM ID. You can implement up to 1,024 instances of a particular BFM component. Then section 19.3 might be of interest too. I remember going through all this (but with verilog) and honestly I didn't find the examples useful at all, but maybe the VHDL one is better or maybe you can make more sense out of it. Note in that API reference section 19.2 includes some info about an example VHDL testbench that uses the Avalon-mm master BFM. So, if there is any I'd really appreciate a link to it. I presume these are basic issues, but I didn't really find any example code of doing this in VHDL. What I did was I added them all into the project, compiled them using This all might be that I've approached adding the files wrong. However, if I try to include altera_avalon_mm_master_bfm.sv, where the functions are, then I get the error that the file isn't a library nor a package. Looking online I see that people using Verilog include only avalon_mm_pkg and verbosity_pkg, but if I do that then ModelSim doesn't recognize any of the functions. However, I'm running into some issues, which are most likely easily solvable, but I don't know where to exactly look, because the API is difficult to understand when using VHDL as a novice.ġ) Can someone tell me what the req_if(bfm_id) stands for in the functions? And what type of input it expects( whether 0/1 or '0'/'1')?Ģ)I don't know what is the correct way of importing the functions into ModelSim. I don't think Modelsim 10.I'm trying to simulate the Avalon Memory Mapped Master Bus Functional Model in Modelsim using VHDL.
#MODELSIM ALTERA VHDL FULL#
in the dialog which opens in the Visibility tab check the "Apply the full visibility to all modules (full debug mode)". Vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRLĪdd wave sim:/tb_packetfile_ctrl/u1/P_clk_inĪdd wave sim:/tb_packetfile_ctrl/u1/P_clk_outĪdd wave sim:/tb_packetfile_ctrl/u1/ResetĪdd wave sim:/tb_packetfile_ctrl/u1/WriteĪdd wave sim:/tb_packetfile_ctrl/u1/last_block ?ġ- Start simulation from the Simulate menu by clicking option "Start Simulation." (not by double clicking on the module).Ģ- In the dialog which opens to ask the model/module to simulate, click on "Optimization Options." button. Is there an alternative way without using the macro (this meansĪdding a wave belatedly when the waveform - editor is already opened)Ĭd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim "add wave sim:/tb_packetfile_ctrl/u1/last_block" If I write the following command in my macro I do not get a wave of These waves are inputs and outputsīut what if I want to view internal signals? For example the internal In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"